The present invention relates generally to fabrication of interconnect, such as copper interconnect for example, within an integrated circuit, and more particularly, to using different types of metal alloys for the seed layer and the conductive fill for filling an interconnect opening to minimize electromigration and void formation within the interconnect.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Thus far, aluminum has been prevalently used for metallization within integrated circuits. However, as the width of metal lines are scaled down to smaller submicron and even nanometer dimensions, aluminum metallization shows electromigration failure. Electromigration failure, which may lead to open and extruded metal lines, is now a commonly recognized problem. Moreover, as dimensions of metal lines further decrease, metal line resistance increases substantially, and this increase in line resistance may adversely affect circuit performance.
Given the concerns of electromigration and line resistance with smaller metal lines and vias, copper is considered a more viable metal for smaller metallization dimensions. Copper has lower bulk resistivity and potentially higher electromigration tolerance than aluminum. Both the lower bulk resistivity and the higher electromigration tolerance improve circuit performance.
Referring to FIG. 1, a cross sectional view is shown of a copper interconnect 102 within a trench 104 formed in an insulating layer 106. The copper interconnect 102 within the insulating layer 106 is formed on a semiconductor wafer 108 such as a silicon substrate as part of an integrated circuit. Because copper is not a volatile metal, copper cannot be easily etched away in a deposition and etching process as typically used for aluminum metallization. Thus, the copper interconnect 102 is typically formed by etching the trench 104 as an opening within the insulating layer 106, and the trench 104 is then filled with copper typically by an electroplating process, as known to one of ordinary skill in the art of integrated circuit fabrication.
Unfortunately, copper is a mid-bandgap impurity in silicon and silicon dioxide. Thus, copper may diffuse easily into these common integrated circuit materials. Referring to FIG. 1, the insulating layer 106 may be comprised of silicon dioxide or a low dielectric constant insulating material such as organic doped silica, as known to one of ordinary skill in the art of integrated circuit fabrication. Copper may easily diffuse into such an insulating layer 106, and this diffusion of copper may degrade the performance of the integrated circuit. Thus, a diffusion barrier material 110 is deposited to surround the copper interconnect 102 within the insulating layer 106 on the sidewalls and the bottom wall of the copper interconnect 102, as known to one of ordinary skill in the art of integrated circuit fabrication. The diffusion barrier material 110 is disposed between the copper interconnect 102 and the insulating layer 106 for preventing diffusion of copper from the copper interconnect 102 to the insulating layer 106 to preserve the integrity of the insulating layer 106.
Further referring to FIG. 1, an encapsulating layer 112 is deposited as a passivation layer to encapsulate the copper interconnect 102, as known to one of ordinary skill in the art of integrated circuit fabrication. The encapsulating layer 112 is typically comprised of a dielectric such as silicon nitride, and copper from the copper interconnect 102 does not easily diffuse into such a dielectric of the encapsulating layer 112.
Referring to FIG. 1, in the prior art, the encapsulating layer 112 of silicon nitride is deposited directly onto an exposed surface of the copper interconnect 102 and the surrounding insulating layer 106 after the exposed surface of the copper interconnect 102 and the surrounding insulating layer 106 are polished to a level surface. Unfortunately, the silicon nitride of the encapsulating layer 112 does not bond well to the copper at the exposed surface of the copper interconnect 102.
Thus, although copper does not diffuse easily through the encapsulating layer 112 of silicon nitride, copper from the copper interconnect 102 laterally drifts from the interface between the copper interconnect 102 and the encapsulating layer 112 of silicon nitride along the bottom surface 114 of the encapsulating layer 112 of silicon nitride because of the weak bonding of the copper interconnect 102 and the encapsulating layer 112 of silicon nitride.
The copper that laterally drifts from the interface between the copper interconnect 102 and the encapsulating layer 112 of silicon nitride along the bottom surface 114 of the encapsulating layer 112 eventually diffuses into the insulating layer 106 to disadvantageously degrade the insulating property of the insulating layer 106 and to possibly degrade the copper interconnect electromigration life-time. Nevertheless, use of copper metallization is desirable for further scaling down integrated circuit dimensions because of the lower bulk resistivity and the higher electromigration tolerance. Thus, a mechanism is desired for preventing the drift of copper from the copper interconnect 102 into the insulating layer 106.
In addition, typically for filling the trench 104 with copper, a seed layer of copper is deposited on the sidewalls and the bottom wall of the trench, and then copper is electroplated from the seed layer to fill the trench 104 in an ECD (electro chemical deposition) process, as known to one of ordinary skill in the art of integrated circuit fabrication. The seed layer of copper is typically deposited by a conformal deposition process such as a PVD (plasma vapor deposition) process or a CVD (chemical vapor deposition) process as known to one of ordinary skill in the art of integrated circuit fabrication. With such conformal deposition processes, referring to FIG. 2, when the aspect ratio (defined as the depth to the width) of an interconnect opening 120 to be filled with copper is relatively large (i.e., greater than 5:1), a seed layer 122 that is deposited on the sidewalls and the bottom wall of the opening 120 may have a significant overhang 124 at the top corners of the interconnect opening 120.
Referring to FIGS. 2 and 3, when copper fill 126 is plated from the seed layer 122, the copper that is plated from the overhang 124 may close off the top of the interconnect opening 120 before a center portion of the interconnect opening 120 is filled with copper to result in formation of a void 128 within the copper fill 126 toward the center of the interconnect opening 120. Such a void 128 disadvantageously increases the resistance of the interconnect and may even contribute to electromigration failure of the interconnect.
Referring to FIG. 4, to minimize the overhang 124 at the top corners of the interconnect opening 120, the seed layer of copper 122 is deposited to be thinner. However, the deposition of the seed layer 122 is not perfectly conformal with the seed layer 122 being even thinner at the sidewalls of the interconnect opening 120. With such a thinner seed layer 122, the thickness of the seed layer 122 may be as small as tens of angstroms at the sidewalls of the interconnect opening 120, and granules 130 of agglomerated copper may form at the sidewalls of the interconnect opening 120. Such granules 130 result in a discontinuous seed layer of copper 122, and when copper is electroplated from such a discontinuous seed layer of copper 122, voids are more likely to form within the copper filling the interconnect opening 120.
Nevertheless, a relatively thin seed layer 122 of copper is desired for minimizing overhang at the top corners of the interconnect opening having high aspect ratio with submicron and even nanometer dimensions. Thus, a mechanism is desired for minimizing formation of granules 130 of agglomerated copper at the sidewalls of the interconnect opening 120 when the seed layer 122 is relatively thin.
Accordingly, in a general aspect of the present invention, a first type of copper alloy is used for formation of the seed layer of copper to minimize formation of the granules of agglomerated copper at the sidewalls of the interconnect opening. In addition, a second type of copper alloy is used to fill the interconnect opening to form an additional encapsulating material at the top surface of the conductive fill of the interconnect opening to prevent drift of copper from the copper interconnect into the surrounding insulating layer.
In one aspect of the present invention, an interconnect opening of an integrated circuit is filled with a conductive fill with the interconnect opening being within an insulating layer on a semiconductor wafer. A seed layer of a first alloy is deposited conformally onto sidewalls and a bottom wall of the interconnect opening. The first alloy is comprised of a first metal dopant in a bulk conductive material. The first metal dopant has a solid solubility in the bulk conductive material that is higher than about 0.09 atomic percent at about room temperature, and the first metal dopant has a concentration in the bulk conductive material of the seed layer that is lower than the solid solubility of the first metal dopant in the bulk conductive material.
The interconnect opening is filled with the bulk conductive material by growing the bulk conductive material from the seed layer to form a conductive fill within the interconnect opening. At least a portion of the conductive fill is comprised of a second alloy with a second metal dopant having a solid solubility in the bulk conductive material that is less than about 0.1 atomic percent at about room temperature, and the second metal dopant has a concentration in the conductive fill that is higher than the solid solubility of the second metal dopant in the bulk conductive material.
Any of the seed layer of the first alloy and the bulk conductive material are polished away from the insulating layer surrounding the interconnect opening such that the conductive fill is contained within the interconnect opening. A thermal anneal is performed to form an additional encapsulating material that covers a top surface of the conductive fill, and the additional encapsulating material is formed from the second metal dopant diffusing out of the conductive fill during the thermal anneal. A layer of bulk passivation material is formed over the additional encapsulating material and the insulating layer.
Use of the first alloy of the seed layer prevents agglomeration of the bulk conductive material of the seed layer at the sidewalls of the interconnect opening. In addition, because the first metal dopant has a relatively high solid solubility, the first metal dopant remains within the seed layer during the thermal anneal. On the other hand, because the second metal dopant has a relatively low solid solubility within the second alloy of the conductive fill, the second metal dopant diffuses out to the top surface of the conductive fill during the thermal anneal to form the additional encapsulating material for preventing drift of material from the conductive fill along the bottom surface of the layer of bulk passivation material and into the surrounding insulating layer.
The present invention may be used to particular advantage when the bulk conductive material is copper, and when the first metal dopant of the first alloy of the copper seed layer is one of silver and zinc. When the bulk conductive material is copper, the second metal dopant of the second alloy of the conductive fill may be one of tantalum, calcium, and cerium. In that case, the additional encapsulating material may be the second metal dopant. Alternatively, when the second metal dopant of the second alloy of the conductive fill is zirconium, the additional encapsulating material may be an intermetallic compound formed from a reaction of the second metal dopant with copper of the conductive fill during the thermal anneal. When the top surface of the conductive fill is exposed to oxygen plasma during the thermal anneal, the additional encapsulating material may be metal oxide formed from a reaction of the oxygen plasma with the second metal dopant during the thermal anneal.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.